Widok standardowy Widok MARC Widok ISBD

Systematic generation of executing programs for processor elements in parallel ASIC or FPGA-based systems and their transformation into VHDL-descriptions of processor element control units / Oleh Masliennikov.

Autor:

Maslennikow, Oleg Politechnika Koszalińska - Wydział Elektroniki, Katedra Inżynierii Komputerowej, 1996 - 2010

Rodzaj materiału:

ArtykułJęzyk: angielski Inny tytuł:

Systematyczne generowanie programów wykonawczych dla elementów procesora równolegle ASIC lub FPGA systemów i ich przekształceniu w VHDL - opis jednostek sterujących elementów procesora

Praca zawiera:

International Conference on Parallel Processing and Applied Mathematics PPAM 2001 (4 ; 2001 ; Nałęczów, Polska) PPAM 2001

W: Parallel processing and applied mathematics : 4th International Conference, PPAM 2001, Naleczow, Poland, September 9-12, 2001. - New York : Springer, 2002. - s. 272-279Streszczenie: In this paper, a method for the systematic generation of executing programs for processor element of parallel ASIC or FPGA-based systems like processor arrays is proposed. In this method, each processor element of an array has separate control unit and is controlled in an autonomous way, based on the executing program received from the host computer before computations. This method allows also to derive the VHDL-desciption of all processor element control units in the behaviorale style.

Egzemplarze ( 0 )
Uwagi ( 1 )

Brak egzemplarzy dla tego rekordu

In this paper, a method for the systematic generation of executing programs for processor element of parallel ASIC or FPGA-based systems like processor arrays is proposed. In this method, each processor element of an array has separate control unit and is controlled in an autonomous way, based on the executing program received from the host computer before computations. This method allows also to derive the VHDL-desciption of all processor element control units in the behaviorale style.