01863naa a2200217 i 4500 11 KOSZ 005 20191005093906.0 151208s2002 -us | f |000 ||eng d BPK KOSZ 005/HR eng USA Maslennikow, Oleg 1996 - 2010. Politechnika Koszalińska - Wydział Elektroniki, Katedra Inżynierii Komputerowej Configurable microcontroller array / O. Masliennikov, J. Shevtshenko, A. Sergyienko. Dane z Informatora o publikowanych wynikach prac naukowo-badawczych w 2002 roku Wydziału Elektroniki. In this paper, the configurable microcontroller array based on the i8051 processor unit (PU) architecture is proposed. The use of well-known PU architecture simplifies the application programming. The designed microcontroller PU core has in 6 times higher instruction implementation speed, and in more than 2.5 times clock frequency than the orginal microcontroller. The proposed techniqu of mapping the program into configurable hardware showed the 1.5-2 - fold hardware minimization. It shows an effective way to speedup the implementation of both computing and control intensive algorithms. Proposed array is very useful in such applications, where logic intensive calculations, or high speed byte handling computations are of demand. For example, such applications are homomorphic image processing, pattern recognition, genetic algorithms, neural nets, etc. Materiały konferencyjne. W : Proceedings International Conference on Paralel Computing in Electrical Engineering IEEE. - Los Alamitos : 2002, IEEE. - s.47-49 0769517307 International Conference on Parallel Computing in Electrical Engineering PARELEC 2002 (2002 ; Warszawa, Polska) PARELEC 2002 ROZ UKD 11 11