01603naa a2200241 i 4500 12 BPK 20191005093906.0 151208s2002 us | f |100 ||eng d BPK eng CHE 621.3.037/.049 Maslennikow, Oleg 1996 - 2010. Politechnika Koszalińska - Wydział Elektroniki, Katedra Inżynierii Komputerowej Implementation of givens QR decomposition in FPGA / Anatoli Sergyienko, Oleg Maslennikov. Dane z Informatora o publikowanych wynikach prac naukowo-badawczych w 2002 roku Wydziału Elektroniki. A new parallel processor structure for Givens QR-decomposition intended for the FPGA implementation is presented. The structure is derived using method of mapping regular algorithms using affine transformations of the algorithm graph. The method supports pipelined processor unit design, and provides efficient hardware utilization. An example of the implementation of the structure in the Xilinx Virtex FPGA devices is presented. Układy logiczne programowalne FPGA. Materiały konferencyjne. W : Parallel processing and applied mathematics : 4th International Conference, PPAM 2001, Naleczow, Poland, September 9-12, 2001. - New York : Springer, 2002. - pp. 453-465 Lecture Notes in Computer Science ; vol. 2328 9783540480860 International Conference on Parallel Processing and Applied Mathematics PPAM 2001 (4 ; 2001 ; Nałęczów, Polska) PPAM 2001 ROZ UKD 12 12