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  <titleInfo>
    <title>Implementation of givens QR decomposition in FPGA</title>
  </titleInfo>
  <name type="personal">
    <namePart>Maslennikow, Oleg</namePart>
    <namePart type="termsOfAddress">Politechnika Koszalińska - Wydział Elektroniki, Katedra Inżynierii Komputerowej</namePart>
    <namePart type="date">1996 - 2010</namePart>
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  <name type="conference">
    <namePart>International Conference on Parallel Processing and Applied Mathematics PPAM 2001 2001 ; Nałęczów, Polska)</namePart>
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  <genre authority="">Materiały konferencyjne.</genre>
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    <dateIssued encoding="marc">2002</dateIssued>
    <issuance>monographic</issuance>
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    <languageTerm authority="iso639-2b" type="code">eng</languageTerm>
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  <abstract>A new parallel processor structure for Givens QR-decomposition intended for the FPGA implementation is presented. The structure is derived using method of mapping regular algorithms using affine transformations of the algorithm graph. The method supports pipelined processor unit design, and provides efficient hardware utilization. An example of the implementation of the structure in the Xilinx Virtex FPGA devices is presented.</abstract>
  <targetAudience authority="marctarget">specialized</targetAudience>
  <note type="statement of responsibility">Anatoli Sergyienko, Oleg Maslennikov.</note>
  <note>Dane z Informatora o publikowanych wynikach prac naukowo-badawczych w 2002 roku Wydziału Elektroniki.</note>
  <subject authority="lcsh">
    <topic>Układy logiczne programowalne FPGA</topic>
  </subject>
  <classification authority="udc">621.3.037/.049</classification>
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    <titleInfo>
      <title>Parallel processing and applied mathematics : 4th International Conference, PPAM  2001, Naleczow, Poland, September 9-12, 2001. -</title>
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    <originInfo>
      <publisher>New York : Springer, 2002. -</publisher>
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    <part>
      <text> pp. 453-465</text>
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