TY  - GEN
AU  - Maslennikow,Oleg, Politechnika Koszalińska - Wydział Elektroniki
ED  - International Conference on Parallel Processing and Applied Mathematics PPAM 2001
TI  - Implementation of givens QR decomposition in FPGA
KW  - Układy logiczne programowalne FPGA
KW  - Materiały konferencyjne
N1  - Dane z Informatora o publikowanych wynikach prac naukowo-badawczych w 2002 roku Wydziału Elektroniki
N2  - A new parallel processor structure for Givens QR-decomposition intended for the FPGA implementation is presented. The structure is derived using method of mapping regular algorithms using affine transformations of the algorithm graph. The method supports pipelined processor unit design, and provides efficient hardware utilization. An example of the implementation of the structure in the Xilinx Virtex FPGA devices is presented
ER  -