01703naa a2200181 i 450000100030000000300090000300500170001200800390002904000210006804100080008904400080009710001230010524502150022824602030044352004960064677302440114271101350138613KOSZ 00520191005093906.0151208s2002    gw  |  |     |100 ||eng  cBPKdKOSZ 005/HR  aeng  aDEU1 aMaslennikow, Olegd1996 - 2010.bPolitechnika Koszalińska - Wydział Elektroniki,cKatedra Inżynierii Komputerowej10aSystematic generation of executing programs for processor elements in parallel ASIC or FPGA-based systems and their transformation into VHDL-descriptions of processor element control units /cOleh Masliennikov.30aSystematyczne generowanie programów wykonawczych dla elementów procesora równolegle ASIC lub FPGA systemów i ich przekształceniu w VHDL - opis jednostek sterujących elementów procesora/  aIn this paper, a method for the systematic generation of executing programs for processor element of parallel ASIC or FPGA-based systems like processor arrays is proposed. In this method, each processor element of an array has separate control unit and is controlled in an autonomous way, based on the executing program received from the host computer before computations. This method allows also to derive the VHDL-desciption of all processor element control units in the behaviorale style.0 iW :tParallel processing and applied mathematics : 4th International Conference, PPAM  2001, Naleczow, Poland, September 9-12, 2001. - dNew York : Springer, 2002. -gs. 272-279kLecture Notes in Computer Science ; vol. 2328z978354048086022aInternational Conference on Parallel Processing and Applied Mathematics PPAM 2001n(4 ;d2001 ;cNałęczów, Polska)pPPAM 2001