01753naa a2200205 i 4500 13 KOSZ 005 20191005093906.0 151208s2002 gw | | |100 ||eng BPK KOSZ 005/HR eng DEU Maslennikow, Oleg 1996 - 2010. Politechnika Koszalińska - Wydział Elektroniki, Katedra Inżynierii Komputerowej Systematic generation of executing programs for processor elements in parallel ASIC or FPGA-based systems and their transformation into VHDL-descriptions of processor element control units / Oleh Masliennikov. Systematyczne generowanie programów wykonawczych dla elementów procesora równolegle ASIC lub FPGA systemów i ich przekształceniu w VHDL - opis jednostek sterujących elementów procesora/ In this paper, a method for the systematic generation of executing programs for processor element of parallel ASIC or FPGA-based systems like processor arrays is proposed. In this method, each processor element of an array has separate control unit and is controlled in an autonomous way, based on the executing program received from the host computer before computations. This method allows also to derive the VHDL-desciption of all processor element control units in the behaviorale style. W : Parallel processing and applied mathematics : 4th International Conference, PPAM 2001, Naleczow, Poland, September 9-12, 2001. - New York : Springer, 2002. - s. 272-279 Lecture Notes in Computer Science ; vol. 2328 9783540480860 International Conference on Parallel Processing and Applied Mathematics PPAM 2001 (4 ; 2001 ; Nałęczów, Polska) PPAM 2001 ROZ UKD 13 13