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  <titleInfo>
    <title>FIR filter soft core generator</title>
  </titleInfo>
  <name type="personal">
    <namePart>Maslennikow, Oleg</namePart>
    <namePart type="termsOfAddress">Politechnika Koszalińska - Wydział Elektroniki, Katedra Inżynierii Komputerowej</namePart>
    <namePart type="date">1996 - 2010</namePart>
    <role>
      <roleTerm authority="marcrelator" type="text">creator</roleTerm>
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  <name type="conference">
    <namePart>RUC 2001 2001 ; Szczecin, Polska).</namePart>
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  <genre authority="">Materiały konferencyjne.</genre>
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    <dateIssued>2001</dateIssued>
    <issuance>monographic</issuance>
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  <language>
    <languageTerm authority="iso639-2b" type="code">eng</languageTerm>
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  <physicalDescription>
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    <extent>s. 167-171</extent>
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  <abstract>A new FIR filter soft core generator is represented which utilizes structural properties of FPGA, minimizes its hardware volume. It provides the design of highly pipelined structures with extremely high clock frequency which are described on VHDL.</abstract>
  <note type="statement of responsibility">A. Sergyienko, V. Vasylienko, O. Maslennikow.</note>
  <note>Dane z Informatora o publikowanych wynikach prac naukowo-badawczych w 2001 roku Wydziału Elektroniki.</note>
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    <titleInfo>
      <title>Materiały IV Konferencji Krajowej "Reprogramowalne układy cyfrowe" RUC. -</title>
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    <part>
      <text>2001, s. 167-172</text>
    </part>
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