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  <titleInfo>
    <title>VHDL models of digital sequential circuits with the current-mode gates</title>
  </titleInfo>
  <name type="personal">
    <namePart>GRETKOWSKI, Dariusz.</namePart>
    <namePart type="termsOfAddress">Politechnika Koszalińska - Wydział Elektroniki, Katedra Systemów Cyfrowego Przetwarzania Sygnałów</namePart>
    <namePart type="date">1996 -</namePart>
    <role>
      <roleTerm authority="marcrelator" type="text">creator</roleTerm>
    </role>
  </name>
  <name type="personal">
    <namePart>KANYEVSKYY, Yuriy.</namePart>
    <namePart type="termsOfAddress">Politechnika Koszalińska - Wydział Elektroniki, Katedra Inżynierii Komputerowej</namePart>
    <namePart type="date">1996 - 2001</namePart>
  </name>
  <name type="personal">
    <namePart>Maslennikow, Oleg</namePart>
    <namePart type="termsOfAddress">Politechnika Koszalińska - Wydział Elektroniki, Katedra Inżynierii Komputerowej</namePart>
    <namePart type="date">1996 - 2010</namePart>
  </name>
  <name type="conference">
    <namePart>MIXDES'2000 2000 ; Gdynia, Polska).</namePart>
  </name>
  <typeOfResource>text</typeOfResource>
  <genre authority="marc">conference publication</genre>
  <genre authority="">Materiały konferencyjne.</genre>
  <originInfo>
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    <dateIssued encoding="marc">2000</dateIssued>
    <issuance>monographic</issuance>
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    <languageTerm authority="iso639-2b" type="code">eng</languageTerm>
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    <form authority="marcform">print</form>
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  <abstract>This paper deals with problems of logical level designing, modelling and simulations of digital, sequential circuits, witch are based on the current mode gates - new digital elements operating with constant, continous power supply current.</abstract>
  <targetAudience authority="marctarget">specialized</targetAudience>
  <note type="statement of responsibility">Dariusz Gretkowski, Oleg Maslennikow, Jerzy Kaniewski.</note>
  <note>Dane z Informatora o publikowanych wynikach prac naukowo-badawczych w 2000 roku Wydziału Elektroniki.</note>
  <subject authority="lcsh">
    <topic>VHDL</topic>
  </subject>
  <relatedItem type="host" displayLabel="W :">
    <titleInfo>
      <title>Proc. of the 7-th International Conference on Mixed Design. -</title>
    </titleInfo>
    <originInfo>
      <publisher>Gdynia, 2000. -</publisher>
    </originInfo>
    <part>
      <text>pp. 281-286</text>
    </part>
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    <recordCreationDate encoding="marc">151204</recordCreationDate>
    <recordChangeDate encoding="iso8601">20191005093907.0</recordChangeDate>
    <recordIdentifier source="KOSZ 005">321</recordIdentifier>
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