<?xml version="1.0" encoding="UTF-8"?>
<record
    xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
    xsi:schemaLocation="http://www.loc.gov/MARC21/slim http://www.loc.gov/standards/marcxml/schema/MARC21slim.xsd"
    xmlns="http://www.loc.gov/MARC21/slim">

  <leader>01572naa a2200253 i 4500</leader>
  <controlfield tag="001">35</controlfield>
  <controlfield tag="003">KOSZ 005</controlfield>
  <controlfield tag="005">20180426110637.0</controlfield>
  <controlfield tag="008">151125s2002    pl     f     |100 0 eng</controlfield>
  <datafield tag="040" ind1=" " ind2=" ">
    <subfield code="c">BPK</subfield>
  </datafield>
  <datafield tag="041" ind1=" " ind2=" ">
    <subfield code="a">eng</subfield>
  </datafield>
  <datafield tag="044" ind1=" " ind2=" ">
    <subfield code="a">POL</subfield>
  </datafield>
  <datafield tag="080" ind1=" " ind2=" ">
    <subfield code="a">621.382.3</subfield>
  </datafield>
  <datafield tag="100" ind1="1" ind2=" ">
    <subfield code="a">SUSZY&#x143;SKI, Robert.</subfield>
    <subfield code="d">1996 - .</subfield>
    <subfield code="b">Politechnika Koszali&#x144;ska - Wydzia&#x142; Elektroniki,</subfield>
    <subfield code="c">Katedra System&#xF3;w Cyfrowego Przetwarzania Sygna&#x142;&#xF3;w</subfield>
  </datafield>
  <datafield tag="245" ind1="1" ind2="0">
    <subfield code="a">The D/A cell for reconfigurable data converter /</subfield>
    <subfield code="c">Robert Suszy&#x144;ski, Bogdan Strzeszewski.</subfield>
  </datafield>
  <datafield tag="500" ind1=" " ind2=" ">
    <subfield code="a">Dane z Informatora o publikowanych wynikach prac naukowo-badawczych w 2002 roku Wydzia&#x142;u Elektroniki.</subfield>
  </datafield>
  <datafield tag="520" ind1=" " ind2=" ">
    <subfield code="a">The papers presents a reconfigurable D/A converters for integrating with FPGA circuits in programmable analogue-digital circuits on a signal die. They have been design as a part of the full custom ASIC CMOS-chip. Reconfigurable D/A converter cells are designed in CMOS AMS CUX 0.6 [micro]m technology. Transistor level simulations are presented to demonstrate this concept. Simulation results prove possibility of realization of field programmable mixed analogue-digital arrays on a single die.</subfield>
  </datafield>
  <datafield tag="650" ind1=" " ind2="0">
    <subfield code="a">Tranzystory.</subfield>
  </datafield>
  <datafield tag="655" ind1=" " ind2="0">
    <subfield code="a">Materia&#x142;y konferencyjne.</subfield>
  </datafield>
  <datafield tag="700" ind1="1" ind2=" ">
    <subfield code="a">STRZESZEWSKI, Bogdan.</subfield>
    <subfield code="d">1996 - .</subfield>
    <subfield code="b">Politechnika Koszali&#x144;ska - Wydzia&#x142; Elektroniki,</subfield>
    <subfield code="c">Katedra System&#xF3;w Cyfrowego Przetwarzania Sygna&#x142;&#xF3;w</subfield>
  </datafield>
  <datafield tag="711" ind1="2" ind2="2">
    <subfield code="a">MIXDES'2002</subfield>
    <subfield code="n">(9 ;</subfield>
    <subfield code="d">2002 ;</subfield>
    <subfield code="c">Wroc&#x142;aw, Polska).</subfield>
    <subfield code="p">MIXDES 2002</subfield>
  </datafield>
  <datafield tag="773" ind1="0" ind2=" ">
    <subfield code="i">W :</subfield>
    <subfield code="t">IX International Conference Mixed Design. -</subfield>
    <subfield code="g">2002, s. 351-354</subfield>
  </datafield>
  <datafield tag="942" ind1=" " ind2=" ">
    <subfield code="c">ROZ</subfield>
    <subfield code="2">UKD</subfield>
  </datafield>
  <datafield tag="999" ind1=" " ind2=" ">
    <subfield code="c">35</subfield>
    <subfield code="d">35</subfield>
  </datafield>
</record>
