A low power digitally error corrected 2.5 bit per stage pipelined A/D converter using current-mode signals

A low power digitally error corrected 2.5 bit per stage pipelined A/D converter using current-mode signals STRZESZEWSKI, Bogdan. Politechnika Koszalińska - Wydział Elektroniki, Katedra Systemów Cyfrowego Przetwarzania Sygnałów 1996 - creator SUSZYŃSKI, Robert. Politechnika Koszalińska - Wydział Elektroniki i Informatyki, Katedra Systemów Cyfrowego Przetwarzania Sygnałów 1996 - WAWRYN, Krzysztof. Politechnika Koszalińska - Wydział Elektroniki i Informatyki, Katedra Systemów Cyfrowego Przetwarzania Sygnałów 1996 - text 2011 continuing eng This paper, presents a novel low power current mode 9 bit pipelined a/d converter. The a/d converter structure is composed of three 2.5 bit stages and one 3 bit stage operating in current mode and a final comparator which converts the analog current signal into a digital voltage signal. All the building blocks of the converter were designed in CMOS AMS 0.35 μm technology, simulated, and then a prototype converter was manufactured and measured to verify the proposed concept. The performances of the converter are compared to performances of known voltage-mode switched-capacitance and current-mode switched-current converter structures. Low power consumption and small chip area are the advantages of the proposed converter. Bogdan Strzeszewski, Robert Suszyński, Krzysztof Wawryn. Elektronika Electronics Original article Original article presents the results of original research or experiment Oryginalny artykuł naukowy Oryginalny artykuł naukowy przedstawia rezultaty oryginalnych badań naukowych lub eksperymentu Pipelined a/d converter; current-mode technique; low power|en Journal of Circuits Systems and Computers. - World Scientific Publ Co Pte Ltd. - 0218-1266 2011, Vol. 20, nr 01, s. 29-43. PBN-ID 160308 20180430121619.0