TY  - SER
AU  - STRZESZEWSKI, Bogdan.
AU  - SUSZYŃSKI, Robert.
AU  - WAWRYN, Krzysztof.
TI  - A low power digitally error corrected 2.5 bit per stage pipelined A/D converter using current-mode signals
PY  - 2011///
KW  - Elektronika
KW  - Electronics
KW  - Original article
KW  - Original article presents the results of original research or experiment
KW  - Oryginalny artykuł naukowy
KW  - Oryginalny artykuł naukowy przedstawia rezultaty oryginalnych badań naukowych lub eksperymentu
KW  - Pipelined a/d converter; current-mode technique; low power|en
N2  - This paper, presents a novel low power current mode 9 bit pipelined a/d converter. The a/d converter structure is composed of three 2.5 bit stages and one 3 bit stage operating in current mode and a final comparator which converts the analog current signal into a digital voltage signal. All the building blocks of the converter were designed in CMOS AMS 0.35 μm technology, simulated, and then a prototype converter was manufactured and measured to verify the proposed concept. The performances of the converter are compared to performances of known voltage-mode switched-capacitance and current-mode switched-current converter structures. Low power consumption and small chip area are the advantages of the proposed converter
ER  -