000			01863naa a2200217 i 4500
001			11
003			KOSZ 005
005			20191005093906.0
008			151208s2002 -us | f |000 ||eng d
040			_cBPK _dKOSZ 005/HR
041			_aeng
044			_aUSA
100			_aMaslennikow, Oleg _d1996 - 2010. _bPolitechnika Koszalińska - Wydział Elektroniki, _cKatedra Inżynierii Komputerowej
245			_aConfigurable microcontroller array / _cO. Masliennikov, J. Shevtshenko, A. Sergyienko.
500			_aDane z Informatora o publikowanych wynikach prac naukowo-badawczych w 2002 roku Wydziału Elektroniki.
520			_aIn this paper, the configurable microcontroller array based on the i8051 processor unit (PU) architecture is proposed. The use of well-known PU architecture simplifies the application programming. The designed microcontroller PU core has in 6 times higher instruction implementation speed, and in more than 2.5 times clock frequency than the orginal microcontroller. The proposed techniqu of mapping the program into configurable hardware showed the 1.5-2 - fold hardware minimization. It shows an effective way to speedup the implementation of both computing and control intensive algorithms. Proposed array is very useful in such applications, where logic intensive calculations, or high speed byte handling computations are of demand. For example, such applications are homomorphic image processing, pattern recognition, genetic algorithms, neural nets, etc.
655		0	_aMateriały konferencyjne.
773	0		_iW : _tProceedings International Conference on Paralel Computing in Electrical Engineering IEEE. - _dLos Alamitos : 2002, IEEE. - _gs.47-49 _z0769517307
711	2	2	_aInternational Conference on Parallel Computing in Electrical Engineering PARELEC 2002 _d(2002 ; _cWarszawa, Polska) _pPARELEC 2002
942			_cROZ _2UKD
999			_c11 _d11