000			01603naa a2200241 i 4500
001			12
003			BPK
005			20191005093906.0
008			151208s2002 us | f |100 ||eng d
040			_cBPK
041			_aeng
044			_aCHE
080			_a621.3.037/.049
100	1		_aMaslennikow, Oleg _d1996 - 2010. _bPolitechnika Koszalińska - Wydział Elektroniki, _cKatedra Inżynierii Komputerowej
245	1	0	_aImplementation of givens QR decomposition in FPGA / _cAnatoli Sergyienko, Oleg Maslennikov.
500			_aDane z Informatora o publikowanych wynikach prac naukowo-badawczych w 2002 roku Wydziału Elektroniki.
520			_aA new parallel processor structure for Givens QR-decomposition intended for the FPGA implementation is presented. The structure is derived using method of mapping regular algorithms using affine transformations of the algorithm graph. The method supports pipelined processor unit design, and provides efficient hardware utilization. An example of the implementation of the structure in the Xilinx Virtex FPGA devices is presented.
650		0	_aUkłady logiczne programowalne FPGA.
655		0	_aMateriały konferencyjne.
773	0		_iW : _tParallel processing and applied mathematics : 4th International Conference, PPAM 2001, Naleczow, Poland, September 9-12, 2001. - _dNew York : Springer, 2002. - _g pp. 453-465 _kLecture Notes in Computer Science ; vol. 2328 _z9783540480860
711	2	2	_aInternational Conference on Parallel Processing and Applied Mathematics PPAM 2001 _n(4 ; _d2001 ; _cNałęczów, Polska) _pPPAM 2001
942			_cROZ _2UKD
999			_c12 _d12