000			01753naa a2200205 i 4500
001			13
003			KOSZ 005
005			20191005093906.0
008			151208s2002 gw | | |100 ||eng
040			_cBPK _dKOSZ 005/HR
041			_aeng
044			_aDEU
100	1		_aMaslennikow, Oleg _d1996 - 2010. _bPolitechnika Koszalińska - Wydział Elektroniki, _cKatedra Inżynierii Komputerowej
245	1	0	_aSystematic generation of executing programs for processor elements in parallel ASIC or FPGA-based systems and their transformation into VHDL-descriptions of processor element control units / _cOleh Masliennikov.
246	3	0	_aSystematyczne generowanie programów wykonawczych dla elementów procesora równolegle ASIC lub FPGA systemów i ich przekształceniu w VHDL - opis jednostek sterujących elementów procesora/
520			_aIn this paper, a method for the systematic generation of executing programs for processor element of parallel ASIC or FPGA-based systems like processor arrays is proposed. In this method, each processor element of an array has separate control unit and is controlled in an autonomous way, based on the executing program received from the host computer before computations. This method allows also to derive the VHDL-desciption of all processor element control units in the behaviorale style.
773	0		_iW : _tParallel processing and applied mathematics : 4th International Conference, PPAM 2001, Naleczow, Poland, September 9-12, 2001. - _dNew York : Springer, 2002. - _gs. 272-279 _kLecture Notes in Computer Science ; vol. 2328 _z9783540480860
711	2	2	_aInternational Conference on Parallel Processing and Applied Mathematics PPAM 2001 _n(4 ; _d2001 ; _cNałęczów, Polska) _pPPAM 2001
942			_cROZ _2UKD
999			_c13 _d13