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Implementation of givens QR decomposition in FPGA / Anatoli Sergyienko, Oleg Maslennikov.

Autor:

Maslennikow, Oleg Politechnika Koszalińska - Wydział Elektroniki, Katedra Inżynierii Komputerowej, 1996 - 2010

Rodzaj materiału:

ArtykułJęzyk: angielski Praca zawiera:

International Conference on Parallel Processing and Applied Mathematics PPAM 2001 (4 ; 2001 ; Nałęczów, Polska) PPAM 2001

Tematy:

Układy logiczne programowalne FPGA

Rodzaj/forma:

Materiały konferencyjne.

W: Parallel processing and applied mathematics : 4th International Conference, PPAM 2001, Naleczow, Poland, September 9-12, 2001. - New York : Springer, 2002. - pp. 453-465Streszczenie: A new parallel processor structure for Givens QR-decomposition intended for the FPGA implementation is presented. The structure is derived using method of mapping regular algorithms using affine transformations of the algorithm graph. The method supports pipelined processor unit design, and provides efficient hardware utilization. An example of the implementation of the structure in the Xilinx Virtex FPGA devices is presented.

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A new parallel processor structure for Givens QR-decomposition intended for the FPGA implementation is presented. The structure is derived using method of mapping regular algorithms using affine transformations of the algorithm graph. The method supports pipelined processor unit design, and provides efficient hardware utilization. An example of the implementation of the structure in the Xilinx Virtex FPGA devices is presented.